Many devices utilize integrated processors, such as microprocessors and digital signal processors, with complex arrangements of logic for performing data processing functions in accord with program instructions. Many applications of these processors, for example in portable devices having battery power supplies, warrant careful control of power consumption, typically, to extend life of a charge in the battery power supply. Many functions or applications of the processor do not require the full processing capability of the processor device, or require the full processing capability only for a very limited time. If fully powered continuously, however, unused logic is unnecessarily consuming power.
Complementary Metal Oxide Semiconductor (CMOS) logic gates have traditionally been very good at minimizing power consumed by idle elements as they only consume dynamic power when a circuit is actively switching. However, they also have a static, or leakage, component to their power consumption. Commonly, the dynamic component has largely outweighed the static. However, in newer deep-submicron technologies, the static component is starting to contribute a significant amount to the overall power consumption. In order to be power efficient, modern devices may need to actively limit the amount of static power dissipated.
To achieve power reduction, for battery-powered embedded applications like cell phones, attempts have been made to power down unused portions of logic, thereby removing the leakage power loss. Some have relied upon software control to turn off unused logic components. For this purpose, instructions in the program may turn certain processor elements on when they will be needed and off when not needed. While this results in power savings, it imposes additional overhead on the software and requires the programmer to actively control various processor functions.
Automated systems may be used to shut down an unused component after a given amount of time. However, cases arise where time-based powering down of a logic element is potentially problematic. Waking or powering up the component can result in additional power consumption. In some cases, it takes more to power-up the element than to just keep the element on for some short period of time. Also, it takes time to power a component back up. The resulting delay or latency in restarting the component my result in processor stalls, which degrades performance.
Therefore, it is desirable to ensure that the component is not repeatedly powered down only to be powered up a short while later. Repeated power-down and power-up may be termed “thrashing.” A need exists for a technique to selectively control power to an element of a processor, so as to effectively reduce power consumption yet avoid undue thrashing.